1. Field of the Invention
The present invention relates to a circuit pattern tape for semiconductor packages, and a semiconductor package produced using the novel circuit pattern tape. More particularly, the present invention relates to a circuit pattern tape that is particularly adapted for use in the wafer-scale production of chip size semiconductor packages.
2. Description of the Related Art
As a result of the recent trend in the consumer and industrial electronics markets toward designs that are higher in performance, yet more compact in size, such as communication devices and computers, a demand has arisen for semiconductor packages that have substantially higher input/output pin densities, yet which are simpler and more compact, for use in such devices.
This demand has resulted in the development of a semiconductor package having a size that is nearly the same as that of the semiconductor chip packaged therein. This style of package is referred to in the industry as a xe2x80x9cchip size,xe2x80x9d or a xe2x80x9cchip scale,xe2x80x9d or a xe2x80x9cchip-on-boardxe2x80x9d semiconductor package. Currently, the demand for such semiconductor packages is increasing.
Chip size semiconductor packages are fabricated at a wafer scale level by laminating a circuit pattern tape having a plurality of individual circuit pattern units in it onto the surface of a semiconductor wafer having a plurality of corresponding individual semiconductor dies, or xe2x80x9cchipxe2x80x9d units, in it, to form an assembly, followed by the application to the laminated assembly of a well-known packaging process involving, typically, a wire bonding process for electrically connecting the circuit patterns of the circuit pattern tape to die pads on the semiconductor chips in the wafer, a resin molding process for encapsulating the wire bonding areas of the wafer within a protective resin envelope, a solder ball attachment process for attaching solder balls that are used as external input/output terminals of the package to the wafer, and lastly, a xe2x80x9csingulationxe2x80x9d process, wherein the processed wafer assembly is cut apart to divide the assembly into a plurality of finished, individual semiconductor packages.
FIG. 16A is a plan view of a conventional circuit pattern tape 10xe2x80x2 for semiconductor packages. A plurality of individual circuit pattern units 11 are formed in the circuit pattern tape, the units corresponding on a one-to-one basis to a plurality of individual chip units 3 formed in a semiconductor wafer 2 (see FIG. 17A). Each circuit pattern unit 11 has its own independent, conductive circuit pattern. An insulative solder mask 19 is formed over selected portions of the conductive circuit patterns on the tape, as described below.
FIG. 16B is a magnified view of the circled portion F of the tape shown in FIG. 16A. In the illustrated portion, four identical circuit pattern units 11 are shown joined together at their edges. In FIG. 16B, the reference numeral 12 denotes conductive traces. The solder mask 19 includes openings in it through which one end of each of the conductive traces 12 is exposed. The exposed end of each conductive trace 12 is connected to a solder ball land 13 to which a solder ball (not shown) is attached. Each conductive trace 12 is connected at its other end to an associated one of a plurality of bond fingers formed within a bond finger region 15. A plurality of such conductive traces 12 form the circuit pattern of each circuit pattern unit 11.
The bond finger regions 15, like the solder ball lands 13, are not covered by the solder mask 19, so that the bond fingers 14 are left exposed. An opening region 16xe2x80x2 is defined within each bond finger formation region 15. The opening regions 16xe2x80x2 are punched to form openings 16 prior to laminating the circuit pattern tape 10xe2x80x2 onto the wafer 2. Die bonding pads 4 (see FIG. 17B) on each semiconductor chip unit 3 are upwardly exposed through an associated one of openings. The exposed die pads are connected to respective bond fingers 14 by means of fine, conductive bonding wires 40 (see FIG. 19).
In FIG. 16B, reference numeral 17 denotes high-current-density xe2x80x9cbusxe2x80x9d lines. The bus lines 17 are used in an electrolytic or electroless plating process to form a nickel (Ni)/gold (Au) plating on the solder ball lands 13 and/or on the bond fingers 14. The Ni/Au plating makes it easy to attach the solder balls (not shown) to the lands 13, and/or to bond the bonding wires (see FIG. 19) to the bond fingers 14, respectively. The bus lines 17 are later removed when the wafer is singulated, or cut, along the singulation lines 21, which disconnects the conductive traces 12 from each other electrically.
When chip size semiconductor packages are fabricated using the conventional circuit pattern tape 10xe2x80x2 described above, it is difficult to accurately determine the cutting line for singulation of the circuit pattern units 11 because the space between adjacent circuit pattern units 11 is extremely narrow. As a result, even when there is only a microscopic error in the determination of the cutting line, the bus lines 17 may be only partially removed. This can result in a problem, in that a number of defective semiconductor packages may be produced as a result.
FIG. 16C is a cross-sectional view taken along the line VIIxe2x80x94VII in FIG. 16A. FIG. 16D is a cross-sectional view taken along the line VIIIxe2x80x94VIII in FIG. 16B. FIGS. 16C and 16D respectively illustrate the cross-sectional structure of the conventional circuit pattern tape 10xe2x80x2. The lowermost layer of the tape structure is an insulating polyimide layer 18. Conductive traces 12 and solder ball lands 13 are formed on the surface of the polyimide layer 18. Bond fingers 14 are also formed on the polyimide layer 18 around the respective openings 16. The solder mask 19 is formed over the conductive traces 12. The solder ball lands 13 and bond fingers 14 are upwardly exposed through openings in the solder mask 19. At the peripheral region of each circuit pattern unit 11, a thin, conductive metal film 12xe2x80x2 is laminated over the polyimide layer 18. The solder mask 19 also covers the thin, conductive metal film 12xe2x80x2.
In the conventional circuit pattern tape 10xe2x80x2 described above, only the bond fingers 14, which receive output signals from an associated semiconductor chip 3 (see FIG. 19), are formed in the bond finger regions 15 of each circuit pattern unit 11, as shown in FIGS. 16B and 16D. For this reason, in order to provide ground bonding of ground signals from respective semiconductor chips, it is necessary to connect together a number of the conductive traces 12 connected to the bond fingers 14, for example, by electrically connecting together a number of the solder ball lands 13. As a result of this, the circuit pattern has a reduced spatial redundancy for the formation of the circuit pattern, i.e., the conductive traces 12, at each of the regions where such a grounding connection is made. Furthermore, the bond fingers that are to be ground-bonded must be disposed at locations that correspond to the ground signal locations. This can severely limit the freedom of design of the circuit tape pattern, and results in a limitation on the number of die bonding pads on the associated semiconductor chips that can be effectively accommodated.
FIG. 17A is a plan view of a typical wafer 2 partitioned into a plurality of semiconductor chip units 3 by singulation lines 21. The singulation lines 21 may be real or imaginary, and typically consist of lines, or xe2x80x9cstreets,xe2x80x9d scribed in the surface of the wafer 2. FIG. 17B is a magnified view of the circled portion G in FIG. 17A. FIGS. 17A and 17B illustrate wire bonding die pads 4 formed on the active surface of each semiconductor chip unit 3. It should be understood that the arrangement of the die pads 4 shown is intended for illustrative purposes only, as the die pads 4 may be arranged in one or more columns.
FIG. 18A is a plan view of the laminated wafer assembly that is obtained prior to the singulation process by laminating the conventional circuit pattern tape 10xe2x80x2 shown in FIG. 16A onto the wafer 2 shown in FIG. 17A, and then applying the above-described packaging processes to it, thereby forming a plurality of connected semiconductor packages 1,xe2x80x2 each having a conventional package structure. FIG. 18B is a magnified view of the circled portion H in FIG. 18A. In FIG. 18B, the openings 16 shown are formed by punching holes in the circuit pattern tape 10xe2x80x2 at its opening regions 16xe2x80x2. After punching, the resultant circuit pattern tape 10xe2x80x2 is laminated onto the wafer 2. After a wire bonding process, a liquid epoxy resin is dispensed into the openings 16 and the bond finger regions 15 of the resultant wafer assembly and then cured, thereby forming protective resin envelopes 50 around the protected elements. Two resin envelopes 50 are formed on each semiconductor package 1xe2x80x2. Each semiconductor package 1xe2x80x2 thus shares a portion of each resin envelope 50 with an adjacent semiconductor package 1xe2x80x2. One singulation line 21 extends centrally across each resin envelope 50. The resin envelopes 50 are adapted to protect the delicate bonding wires 40, the bond fingers 14, the die bonding pads 4, and their adjacent surfaces from harmful environmental elements, for example, moisture. After the formation of the resin envelopes 50, solder balls 60 (see FIG. 19), which serve as external input/output terminals of the packages, are attached to associated solder ball lands 13, respectively.
Semiconductor packages fabricated with the conventional circuit pattern tape 10xe2x80x2 described above frequently experience a problem during the singulation process. This problem relates to the fact that the singulation lines 21 on the wafer 2 are not visible because, even though the polyimide layer 18 and the adhesive layer 30 are semitransparent, the solder mask 19 and circuit patterns of the circuit pattern tape 10xe2x80x2 are opaque. To overcome this obstacle, the circuit pattern tape 10xe2x80x2 is also provided with singulation lines 21. However, where the circuit pattern tape 10xe2x80x2, which is laminated on the wafer 2, exhibits a relatively high amount of stretching before or during the lamination process, it is very difficult to determine the singulation position of each circuit pattern unit 11 accurately relative to its associated semiconductor chip unit 3 without some positional error arising. For this reason, it is difficult to achieve consistent, accurate singulation of semiconductor packages 1xe2x80x2 that have a consistently accurate and standard size. This results in a reduced yield of semiconductor packages from the wafer.
The process for laminating the conventional circuit pattern tape 10xe2x80x2 to the wafer 2 is carried out at a high temperature. This creates another problem, in the case of a conventional circuit pattern tape 10xe2x80x2 having a non-uniform distribution of the conductive metal forming the circuit pattern, in that voids are easily formed in the circuit pattern tape 10xe2x80x2 due to the relatively high difference between the respective thermal coefficients of expansion of the conductive metal and the resin material of the polyimide layer 18 and/or the solder mask 19.
Moreover, a xe2x80x9cbowingxe2x80x9d phenomenon can occur in the wafer assembly when the wafer 2 is laminated with the conventional circuit pattern tape 10xe2x80x2 at a high temperature, and the assembly then returned to room temperature. This problem also results from the relatively large differences between the respective thermal coefficients of expansion of the conductive metal and the resin material of the polyimide layer 18 and/or the solder mask 19. This bowing phenomenon may become quite severe when the conventional circuit pattern tape 10xe2x80x2 described above is used. This is because the conventional circuit pattern tape 10xe2x80x2 has the thin, planar, conductive metal film 12xe2x80x2 described above, which has a relatively large area, interposed between the polyimide layer 18 and the solder mask 19. The bowing phenomenon makes it difficult to attach the circuit pattern tape 10xe2x80x2 to the wafer in an accurate, xe2x80x9cflatxe2x80x9d state. Furthermore, the bowing makes the smooth implementation of sequent processes difficult. As a result, an unacceptably high number of defective semiconductor packages may be produced from the wafer.
Yet another problem is involved in the manufacture of semiconductor packages using the conventional circuit pattern tape 10xe2x80x2 described above. This problem relates to the fact that, when a liquid encapsulation material exhibiting a relatively high degree of xe2x80x9cflowability,xe2x80x9d such as a liquid epoxy resin, is dispensed into the openings 16, it can easily overflow the openings and spill out onto the laminated assembly. If the overflowing liquid epoxy material reaches the exposed solder ball lands 13, it renders it practically impossible to attach solder balls 60 to them. Alternately, a short circuit can easily occur between adjacent solder balls 60 and solder ball lands 13. This results in defective semiconductor packages.
In an effort to prevent the overflow of liquid encapsulation material, it has been proposed to increase the thickness of the solder mask 19. However, this is not an effective solution to the problem because it is very difficult to control the diameter of each solder ball land 13, as defined by an opening in the thicker solder mask 19. Furthermore, it is difficult to control the height of each solder ball 60 uniformly because of the greater depth of the solder ball lands 13. This can result in either a short circuit or an open circuit between the solder balls 60 and the electrodes of a mother board (not shown) to which the associated semiconductor package is mounted. Therefore, to prevent an overflow of the liquid encapsulation material, it is more preferable to dispense a very accurately metered amount of liquid encapsulation material into the openings 16 of the circuit pattern tape 10xe2x80x2. However, as a practical matter, this is difficult, particularly where the encapsulation material has a relatively high viscosity.
FIG. 18C is a cross-sectional view through the wafer assembly taken along the line IXxe2x80x94IX in FIG. 18B. As shown in FIG. 18C, a plurality of semiconductor packages 1xe2x80x2 having a conventional structure is formed in the wafer assembly. As described above, adjacent semiconductor packages share one resin envelope 50 with each other. A singulation line 21 extends centrally across each resin envelope 50. The semiconductor packages 1xe2x80x2 are cut, or singulated, into individual packages along the singulation lines 21. In a typical singulation process, the semiconductor wafer 2, the circuit pattern tape 10xe2x80x2 and the resin envelopes 50 are cut through simultaneously, usually by sawing.
During the singulation process, the rotational speed and feed rate of the saw blade necessary to cut through the resin envelopes 50 must be greater than that used to cut through the wafer 2 alone because the resin envelopes 50 have different physical characteristics and a higher rupture strength than that of the wafer, which is typically made of silicon. For this reason, when both the resin envelopes 50 and the wafer 2 are sawn simultaneously, an excessive sawing force is applied to the wafer 2 by the saw blade, thereby causing a chipping phenomenon in the wafer in which the sawn halves of the wafer 2 are chipped along the kerf of the saw. This chipping results in problems, in that cracks can be formed at the singulation surfaces of the semiconductor packages 1xe2x80x2 that provide paths for penetration of harmful moisture or other foreign contaminants into the semiconductor packages 1xe2x80x2. As a result, the life span of the packages 1xe2x80x2 may be substantially reduced. Where the cracks caused by chipping are relatively wide, defective semiconductor packages 1xe2x80x2 result. For example, the semiconductor packages 1xe2x80x2 may function unreliably, or they may be rendered totally inoperable.
FIG. 19 is a cross-sectional view illustrating a conventional semiconductor package 1xe2x80x2 fabricated using the conventional circuit pattern tape 10xe2x80x2 shown in FIG. 16A. Referring to FIG. 19, the circuit pattern tape 10xe2x80x2 is laminated on a semiconductor chip 3 in such a fashion that the adhesive layer 30 is interposed between the semiconductor chip 3 and the circuit pattern tape 10xe2x80x2. An opening 16 is centrally formed at the semiconductor package 1xe2x80x2. Die pads 4 on the chip 3 are arranged in the opening 16. The circuit pattern tape 10xe2x80x2 consists of a polyimide layer 18, a circuit pattern, and a solder mask layer 19 arranged in ascending order. The circuit pattern consists of a plurality of conductive traces, each formed with one solder ball land 13 and a bond finger 14. The die pads 4 are electrically coupled to associated bond fingers 14 by means of fine, conductive bonding wires 40. A resin envelope 50 is formed in the region that includes the opening 16, the bond fingers, and the bonding wires 40. Solder balls 60 are shown attached to each solder ball land 13 as external input/output terminals of the package 1xe2x80x2.
The present invention provides a circuit pattern tape that effectively eliminates wafer chipping during package singulation by the provision of a resin envelope formation region on the tape that does not intersect the singulation lines of the circuit pattern tape and the wafer.
The circuit pattern tape of this invention also effectively prevents or substantially inhibits the formation of voids during lamination of the tape to a wafer by the provision of a first dummy pattern on the tape adapted to provide a uniform distribution of the conductive metal on the tape from which the circuit patterns are formed.
The present invention also provides a circuit pattern tape capable of precisely locating singulation lines on the laminated wafer-tape assembly by the provision of singulation line locating grooves in the tape, each of which is located in a region where four adjacent circuit pattern units join together.
The circuit pattern tape of the invention also effectively prevents or substantially reduces the bowing phenomenon occurring during a high temperature lamination process, or during subsequent fabrication processes, caused by the use of materials having dissimilar thermal coefficients of expansion, by the provision of a second dummy pattern disposed between a central circuit pattern unit portion of the tape and a peripheral portion arranged around the central portion, and/or a bowing-prevention element that is not coated with a solder mask, and/or by the provision of a second dummy pattern arranged at the peripheral portion of the tape.
The present invention also provides a circuit pattern tape that avoids a reduced spatial redundancy in the pattern units, caused by the need to interconnect a large number of conductive traces for grounding purposes, by the provision of ground fingers formed at bond finger formation regions located on opposite sides of an opening formation region.
The present invention also provides a circuit pattern tape that permits the easy and complete removal of plating bus lines, even when there is a slight error involved in the singulation process, by the provision of bus lines that are located in the opening formation region inside the bond finger formation regions.
The circuit pattern tape of the present invention also prevents the overflow of liquid encapsulating material during the formation of protective resin envelopes by the provision of one or more liquid encapsulant retaining dams located adjacent to the resin envelope formation regions.
The invention also provides a chip size semiconductor package in which any one or more of the above-described advances over the prior art are readily achieved.